Performance Of Magnetic Tunnel Junctions Research Articles

Intermixing of iron and cobalt with oxygen-rich magnesium oxide in CoFeB/MgO/CoFeB magnetic tunneling junctions

Atomic-scale spectroscopic imaging of sputtered magnetic tunnel junction structures with a thick oxygen-rich MgO barrier reveals the diffusion of iron and cobalt into the MgO barrier from CoFeB electrodes. First principles calculations are performed to (1) confirm that Fe diffusion through Mg vacancies is energetically favorable, (2) quantify the reduction of interfacial perpendicular magnetic anisotropy due to Fe diffusion into MgO, and (3) predict that the presence of Fe impurities in MgO causes an increased leakage and a tunneling magnetoresistance decrease. Through the chemical shift of the Fe L3 edge and the peak ratio Fe L3/Fe L2 measured by electron energy loss spectroscopy, we suggest that, within MgO, iron with mixed oxidation state Fe2+ and Fe3+ or higher is found in the as-grown structure, which is reduced by annealing to Fe2+. These results indicate that the stoichiometry of as-deposited MgO barrier layers plays an important role in controlling the microstructure and optimizing the performance of magnetic tunnel junctions.

Perpendicular magnetic tunnel junctions based on half-metallic NiCo2O4

Spin polarization and magnetic anisotropy are key properties that determine the performance of magnetic tunnel junctions (MTJs), which are utilized in various spintronic devices. Although materials that have both high spin polarization and sufficient perpendicular magnetic anisotropy are desirable for further developments of MTJs, such materials are rare because electronic structures necessary for achieving these two properties are distinct. Here, we experimentally show the inverse spinel ferrimagnet NiCo2O4 (NCO), whose band structure is theoretically predicted to be half-metallic, has both high spin polarization and perpendicular magnetic anisotropy. Perpendicular MTJs with NCO magnetic electrodes exhibit magnetoresistance up to 230%, indicating that the spin polarization of perpendicularly magnetized NCO is as high as −73%. Our experimental results demonstrate the potential of NCO as a half-metal with perpendicular magnetic anisotropy, which will lead to new paradigms for designing and developing all-oxide spintronic devices.

Interfacial Perpendicular Magnetic Anisotropy in Magnetic Tunnel Junctions Comprising CoFeB with FeNiSiB Layers

Controlling ferromagnetic thickness (t) and properties such as saturation magnetization (Ms) and effective magnetic anisotropy constant (Keff) has been regarded as critical for the performance of magnetic tunnel junctions (MTJs) with interfacial perpendicular magnetic anisotropy. Here, we report the effects of hybridizing a CoFeB layer with a FeNiSiB layer as part of a magnetic free layer structure. We deposited thin film stacks by magnetron sputtering on Si wafers with thermal oxides and carried out post-deposition heat treatment at 300 °C for 1 h in a vacuum under a magnetic field. We found that Ms and Keff could be tuned by adding a layer of amorphous FeNiSiB. While the Ms and Keff values were modified, the tunneling magnetoresistance (TMR) ratios of the MTJs were maintained, even though the CoFeB thickness was decreased by half. Moreover, an asymmetric bias voltage dependence of TMR was suppressed in the MTJs with FeNiSiB/CoFeB hybrid free layers due to improvements in the interface quality between the CoFeB/MgO interfaces.

Study on the effect of re-deposition induced by ion beam etching on MTJ performances

Magnetic tunnel junction (MTJ) as a key spintronics device can be used for the high-sensitivity magnetic field sensor and high-density non-volatile magnetic random access memory (MRAM). To obtain a high tunneling magnetoresistance (TMR), precise control of the etching process for MTJs is an essential step. In order to investigate the effect of the etching angle on the performance of MTJ devices, a series of MTJ pillars are fabricated by etching with the incidence angle of 10°, 20° and 30°. The prepared samples are characterized by the optical microscopy and SEM, and the R-H curves are also measured and then statistically analyzed. The results reveal that the performance of the MTJ is strongly affected by the IBE process, displaying the uniformity of the pillars edge and MTJ performance will improve as well with the increase of the etching angle. Then, a simplified model based on the re-deposition effect of the etching process is established to explain the experimental phenomena. Furthermore, a newly defined material parameter is introduced in this model and obtained with fitting the experimental results. This proves a valuable way to evaluate the quality of the MTJ stack film without the interference of the device fabrication process.

Perpendicular magnetic tunnel junction performance under mechanical strain

In this work, we investigate effect of the mechanical stress on the performance of magnetic tunnel junctions with perpendicular magnetic anisotropy. We developed a 4-point bending setup that allows us to apply a constant stress over a large substrate area with access to electrical measurements and an external magnetic field. This setup enables us to measure key device performance parameters, such as tunnel magnetoresistance, switching current (Ic50%), and thermal stability (Δ), as a function of applied stress. We find that variations in these parameters are negligible: less than 2% over the entire measured range between the zero stress condition and the maximum stress at the point of wafer breakage.

(Invited) Interface Control of Advanced Electronic Devices - High-k/Metal Gate System and Magnetic Tunneling Junction

With the scaling of electronic devices, interface control of the constituent materials has become more and more important. Several key issues and related topics are taken up and reviewed with respect to logic and memory devices. The key issues are interface control in high-k/metal gate system for logic application and magnetic tunneling junction for memory application. High-k/Metal Gate System [1] In accordance with the requirement of CMOS scaling, replacement of thermally grown SiO2 gate dielectric with other dielectric materials with higher dielectric constant (k) has become imperative to reduce the equivalent oxide thickness (EOT) to achieve higher drivability of FET. Key factors on Hf-based high-k/metal gate (HK/MG) CMOS technology based on conventional gate first process for low operational power application are overviewed. Work-function (WF) tuning derived from ionic property of high-k material, process cost, EOT scaling with low gate leakage current are issues to be overcome. Among them, the key issue is how to control the atomic distribution in the Hf-based HK/MG system, which is absolutely requisite for WF tuning and EOT scaling. Interpretation of effective work-function (WF): For conventional gate first process, due to the interfacial reaction, the Fermi level is pinned and the WF increases with decreasing the EOT. In addition to this, due to the fixed charge in the high-k dielectric, the WF is also modulated, hence the effective WF (eWF) changes. The effect of the fixed charge is rather complicated due to an oxygen vacancy behavior in HK. Consequently, the eWF results in the “roll-off” behavior caused by the (+) charge induced by the oxygen vacancy. When the oxygen increases, i.e., (-) charge increases in the HK, the obtained WF tends to roll-up. In contrast, it tends to roll-off for more (+) charge induced by oxygen vacancy, Vo 2+in the HK. Formation process of Hf-based high-k (HK): Generally, HK is deposited by metal-organic chemical vapor deposition (MOCVD) or atomic layer deposition (ALD), however, HK dielectric formation by oxidizing a preliminarily sputtered metallic-Hf is reasonable approach for fabricating the HK gate stack in a very pure form with less water content across the wafer. And in a very important thing, by controlling the oxidation time, this process can provide precise thickness control of the interfacial layer (IL) including “zero IL” with excellent uniformity. Magnetic Tunneling Junction A magnetic tunnel junction (MTJ) for spin-transfer-torque (STT) switching is a promising building block of non-volatile working memory embedded in very large scale integrated circuits (VLSIs) because of its potential to reduce a power consumption by replacing the conventional volatile cache memories. Among many materials, a CoFeB/MgO/CoFeB stack structure has attracted much attention as a candidate of MTJ embedded in VLSIs because of its high tunnel magnetoresistance (TMR) ratio caused by a perpendicular magnetic easy axis. And what is better, this MTJ has a potential for high integration into VLSIs down to a junction size of 1X nm regime. To improve the MTJ performance, crystal structure of the CoFeB/MgO interface is a crucial issue as well as B behavior during the process treatment. Redox reaction:  As an example of the interfacial reaction, a redox reaction was observed at the surface of Ta/CoFeB/MgO/CoFeB MTJ stack after annealing up to 400℃ for 1 h in vacuum, by angle-resolved X-ray photoelectron spectroscopy (XPS). For 1nm-thick tantalum capping layer of the as-deposited stack sample, both the tantalum layer and the surface of the CoFeB layer underneath the tantalum layer were naturally oxidized. By comparison of the Co 2p and Fe 2p spectra with respect to as-deposited and annealed samples, reduction of the naturally oxidized cobalt and iron atoms was found to occur at the surface of the CoFeB layer. This reduction reaction was more significant at higher annealing temperature. Oxidized cobalt and iron were found to be reduced by boron atoms that diffused toward the surface of the top CoFeB layer. By means of naturally oxidized surface of the CoFeB layer formed on SiO2, the redox reaction behavior after annealing was confirmed by angle-resolved XPS analysis[2]. This redox reaction is thermodynamically reasonable according to the Ellingham diagram. (This work is supported by Industrial Affiliation on the STT-MRAM program in CIES Consortium and ACCEL project under JST.) [1] M. Niwa (2013), Chapter 4, High Permittivity Gate Dielectric Materials, Edited by S. Karr, Springer Series in Advanced Microelectronics 43 , pp. 191-234. [2] S. Sato et al., Appl. Phys. Lett. 196, 142407 (2015).

Etching Methods for STT-MRAM

Spin-transfer torque [1] MRAM (STT-MRAM) continues to be the subject of intense investigation due to its scalability and excellent endurance. Initially explored mainly as a DRAM replacement, STT-MRAM with perpendicularly magnetized materials is now targeted as a nonvolatile memory, medium-performance replacement for mobile applications, and more long term as a fast, dense, cache memory. This talk will review MRAM magnetic stack etching methods and related aspects of integration, with particular reference to STT-MRAM. An STT-MRAM memory cell, which consists of a magnetic tunnel junction (MTJ) and a transistor, has the attractive property that if the critical current density for spin-torque switching (Jc) remains constant, then the critical current for MTJ switching (Ic) will scale as λ2, where λ is MTJ diameter . Thus, scaling is highly desirable for STT-MRAM. A significant research effort is also being devoted to developing MTJs with perpendicular magnetic anisotropy (PMA) materials [2] to achieve acceptably low switching currents, e.g., < 25 uA. Scaling is not without challenges, however, and the STT-MTJ arrays must, e.g., exhibit sufficient statistical margins between reading and writing operations, and must satisfy other key design properties including, a) sufficient TMR for the read signal, and b) a high enough energy barrier for up to 10 years of data retention. It has been found that fabrication processes like MTJ etching play key roles in MTJ performance to realize the full potential of newly-developed PMA materials, e.g., the ability to approach the resistance-area product RA measured by current-in-plane tunneling (CIPT) [3] on unprocessed MRAM stacks. The semiconductor industry seems to be preparing for large-scale manufacturing of STT-MRAM, by converging on an IBE-centered etching approach, followed by in situencapsulation. Minimizing metallic redeposition on the edge of the tunnel barrier during etching, and of edge-related magnetic damage, are key challenges in STTM patterning using IBE. Ohsawa et al. [4] showed that a typical MRAM IBE etching energy, e.g., 200 eV, causes a damage layer several monolayers thick at the patterned surface, suggesting that lower beam energies would be necessary during etching, or at least in the final damage-removal step. Confirming the promise of IBE, Samsung researchers Song et al. [5] recently reported high yields for an embedded STT-MRAM, patterned using IBE, with 8-Mbit density and a cell size of 0.0364 sq. micron. At IBM, following conventional 193 nm lithography, we have typically employed a RIE etch to pattern a Ta-based MTJ hardmask, stopping on a protective cap layer, which is then followed by MRAM stack etching using a combination of a MeOH-based RIE and IBE. Using arrays of different lithographically-printed MTJ mask diameters, final etched device sizes ranging from a high of about 100 nm down to 10 nm or less are typically obtained, as confirmed by TEM [6, 7]. Using this patterning approach, we demonstrated good STT performance down to 10-6 write-error-rate (WER) in a wide range of device sizes from 50 nm to 11 nm for a specific PMA STT-MRAM stack, for a statistically relevant sample of more than 650 devices [7]. We further demonstrated an individual 11 nm device switching down to WER = 7*10-10at 10 ns using only 7.5 uA current. [1] J. C. Slonczewski, J. Magn. Magn. Mater.,159, L1 (1996). [2] For ex., D. C. Worledge et al., IEDM Tech. Dig., 296 (2010); S. Ikeda et al., Nature Mater., 9, 721 (2010). [3] D. C. Worledge and P. L. Trouilloud, Appl. Phys. Lett., 83, 84 (2003). [4] Y. Ohsawa et al., IEEE Trans. Magn., 52, 1 (2016). [5] Y.J. Song et al., IEDM, paper 27.2, (2016). [6] M. Gajek et al., Appl. Phys. Lett., 100, 132408 (2012). [7] J. J. Nowak et al., IEEE Magn. Lett., 7, 1 (2016). Acknowledgements   We wish to thank E. Galligan, for technical support. The authors gratefully acknowledge the efforts of the staff of the Microelectronics Research Laboratory (MRL) at the IBM T. J. Watson Research Center, where the magnetic device layers were fabricated.

The need for control of magnetic parameters for energy efficient performance of magnetic tunnel junctions

Optimizing energy performance of Magnetic Tunnel Junctions (MTJs) is the key for embedding Spin Transfer Torque-Random Access Memory (STT-RAM) in low power circuits. Due to the complex interdependencies of the parameters and variables of the device operating energy, it is important to analyse parameters with most effective control of MTJ power. The impact of threshold current density, Jco, on the energy and the impact of HK on Jco are studied analytically, following the expressions that stem from Landau-Lifshitz-Gilbert-Slonczewski (LLGS-STT) model. In addition, the impact of other magnetic material parameters, such as Ms, and geometric parameters such as tfree and λ is discussed. Device modelling study was conducted to analyse the impact at the circuit level. Nano-magnetism simulation based on NMAGTM package was conducted to analyse the impact of controlling HK on the switching dynamics of the film.

Towards sub-nanometer real-space observation of spin and orbital magnetism at the Fe/MgO interface

While the performance of magnetic tunnel junctions based on metal/oxide interfaces is determined by hybridization, charge transfer, and magnetic properties at the interface, there are currently only limited experimental techniques with sufficient spatial resolution to directly observe these effects simultaneously in real-space. In this letter, we demonstrate an experimental method based on Electron Magnetic Circular Dichroism (EMCD) that will allow researchers to simultaneously map magnetic transitions and valency in real-space over interfacial cross-sections with sub-nanometer spatial resolution. We apply this method to an Fe/MgO bilayer system, observing a significant enhancement in the orbital to spin moment ratio that is strongly localized to the interfacial region. Through the use of first-principles calculations, multivariate statistical analysis, and Electron Energy-Loss Spectroscopy (EELS), we explore the extent to which this enhancement can be attributed to emergent magnetism due to structural confinement at the interface. We conclude that this method has the potential to directly visualize spin and orbital moments at buried interfaces in magnetic systems with unprecedented spatial resolution.

Scalability of Magnetic Tunnel Junctions Patterned by a Novel Plasma Ribbon Beam Etching Process on 300 mm Wafers

The performance of magnetic tunnel junction (MTJ) over its critical dimension (CD) is critical to the application of spin transfer torque magnetic random access memory. To study the CD scaling effects, we designed a series of MTJ CDs and used a novel plasma ribbon beam etching (PRBE) process to pattern the MTJs. PRBE has constant beam density and beam angle distribution across a 300 mm wafer. The MTJs patterned by PRBE demonstrated low tunneling magnetoresistance degradation from 145% on blanket films to $\sim 130$ % for MTJ CDs ranging from 100 to 20 nm. At 20 nm, MTJ switching current was down to 20 $\mu \text{A}$ , and the thermal stability factor was still above 40, demonstrating good device scalability.

Effects of post-growth annealing in a CoFeB/MgO/CoFeB trilayer structure

CoFeB/MgO/CoFeB tri-layer thin-film stacks have been widely used in the design of STT-RAM devices as functional magnetic-tunnel-junction (MTJ) structures. The materials properties of the CoFeB and MgO layers, including composition and lattice quality, have been extensively researched from the stand point of optimizing for the best MTJ performance. On the other hand, post-growth annealing is required for the MTJ structure to acquire its functional property, i.e. its TMR performance. In this work, we have studied the various possible effects resulting from the post-growth annealing process. Specifically, we show that the post-growth annealing causes boron in the top and bottom CoFeB layers to migrate into the adjacent Ta layers as well as deterioration in lattice quality of the MgO layer. Furthermore, we evaluate other effects that could be possibly induced during the annealing process, including Ta diffusion and layer intermixing in the CoFeB/MgO/CoFeB tri-layer structure. The post-growth annealing causes little change in the Ta diffusion and the layer intermixing. These annealing effects were also evaluated with respect to variations in the MgO growth process; more specifically, an additional natural oxidation treatment during the MgO layer deposition and the insertion of a Fe layer before the MgO layer. Our results indicate that the addition of a natural oxidation process during the MgO deposition process and the insertion of a thin-layer of Fe before the MgO layer both lead to a reduction in the layer intermixing between the MgO and the CoFeB layer and to an improvement in MgO lattice quality. We also show that the post-growth annealing does not alter the beneficial effect of these MgO growth process modifications.

Ab-initio investigation of electronic and magnetic properties of the 18-valence-electron fully-compensated ferrimagnetic (CrV)XZ Heusler compounds: A prototype for spin-filter materials

Spin-filter materials are magnetic semiconductors susceptible of improving the performance of magnetic tunnel junction based spintronic devices. Using state-of-the-art ab initio electronic structure calculations, we exploit the electronic and magnetic properties of (CrV)XZ quaternary Heusler compounds having 18 valence electrons per formula unit. All compounds under study have been found to combine fully-compensated ferrimagnetism to magnetic semiconducting behavior and some are even gapless or spin-gapless semiconductors. Our results pave the way for incorporating these compounds in spintronic and magnetoelectronic devices.

(Keynote) Status and Challenges in Spin-Transfer Torque MRAM Technology

Spin-transfer torque magnetic random access memory (STT-MRAM) has been considered as a promising candidate for next generation non-volatile memory due to a combination of fast speed, high endurance, excellent scalability, and ease of integration with the standard CMOS processes. While feasibility demonstrations used magnetic tunnel junction (MTJ) devices with an in-plane magnetization, significant advances in materials allowed implementation of the perpendicular MTJ design, which provides the best long-term scalability for STT-MRAM beyond 20 nm. Despite significant progress, there are many remaining hurdles in the productization of STT-MRAM. They are stemming from a set of requirements imposed on the MTJ performance: simultaneously low writing current/voltage and high thermal stability, high magneto-resistance at low RA (resistance and area product) value, low error rates and high endurance cycles. We will discuss the inter-dependencies of these parameters, and show how they are affected by varying magnetic properties of the MTJ stack layers. In particular, we study impact of the free layer anisotropy, magnetic moment, thickness, and Gilbert damping on writing current and thermal stability. In this presentation, we report our progress in meeting these requirements and our development approaches for future challenges. ----------------------------------------------------------------------------------------------------------------------------------------------- Mohamad Krounbi has over 25 years of experience in magnetic recording technology and recording head process and design innovations. While at IBM from 1978 to 1997, he played a leading role in the development and production of the magneto resistive heads from MR to GMR and TMR generations of products. Mohamad contributed to major breakthroughs in design, process, and integration of heads and media in the HDD industry. He held executive positions at IBM, Western Digital, and Hitachi Global Storage Technology (HGST). Mohamad holds over 50 US patents and co-authored numerous scientific publications in magnetic recording and fundamental materials and polymer research. He received numerous outstanding innovation and contribution awards while at IBM and was elected to the IBM academy of technology in 1995.  At HGST he was awarded the President’s technology award for the development and launch of the first perpendicular magnetic recording product.  In 2010, Mohamad joined Grandis, Inc. as the CTO and Senior Vice President of  technology development and operations.  Mohamad is currently the CTO and Senior Vice President of Samsung’s New Memory Technology Laboratory in the US ( NMT Lab).  Mohamad has a BS in Physics from Hagazian College in Beirut Lebanon and a MS in Physics from San Jose State University.

Compact thermal modeling of spin transfer torque magnetic tunnel junction

Magnetic tunnel junction (MTJ) with spin transfer torque (STT) switching method features fast speed, low power, great scalability and high compatibility with conventional CMOS process. Nevertheless, its magnetic and electrical properties can be easily influenced by operation temperature and self-heating effect, which further results in performance degradation and reliability issues of MTJ based memories and logic circuits. This paper investigates the behaviors of MTJ under different temperatures and further proposes a model in consideration of temperature impact on performance of MTJ, which can be used to optimize the design of STT-MRAM in terms of dynamic operations and temperature tolerance.

Comprehensive noise characterisation of magnetic tunnel junction sensors for optimising sensor performance and temperature detection

Noise performance of magnetic tunnel junction (MTJ) sensors is impacted by various factors including junction structure, post-deposition treatment, and operating parameters. The optimisation of these factors can lead to a better MTJ sensor design with minimised noise level and enhanced detectivity for functioning as a magnetometer. In this paper, the authors studied the influence of several parameters (bias voltage, temperature, magnetic field, and junction area) on the noise performance of MTJ sensors. Relatively high bias voltage and low ambient temperature were suggested to be helpful in reducing the electronic 1/f noise. A mechanism of utilising MTJ as a temperature sensor by making use of the mid-frequency noise (from 10.0 kHz to 22.8 kHz) was proposed. The relation between temperature and noise power was obtained by numerically fitting the measured noise power with an equation composing of three components representing background noise, intertwined thermal and shot noise, and non-linear noise source, respectively. Temperature of the junction could be determined by measuring the mid-frequency noise power at certain bias voltage and substituting it into the equation. This provides a possible route of using a MTJ as a multifunctional sensor for sensing both magnetic field and temperature.

Derivation of the spin Hamiltonians for Fe in MgO

A method to calculate the effective spin Hamiltonian for a transition metal impurity in a non-magnetic insulating host is presented and applied to the paradigmatic case of Fe in MgO. In the first step we calculate the electronic structure employing standard density functional theory (DFT), based on generalized gradient approximation (GGA), using plane waves as a basis set. The corresponding basis of atomic-like maximally localized Wannier functions is derived and used to represent the DFT Hamiltonian, resulting in a tight-binding model for the atomic orbitals of the magnetic impurity. The third step is to solve, by exact numerical diagonalization, the N electron problem in the open shell of the magnetic atom, including both effects of spin–orbit and Coulomb repulsion. Finally, the low energy sector of this multi-electron Hamiltonian is mapped into effective spin models that, in addition to the spin matrices S, can also include the orbital angular momentum L when appropriate. We successfully apply the method to Fe in MgO, considering both the undistorted and Jahn–Teller (JT) distorted cases. Implications for the influence of Fe impurities on the performance of magnetic tunnel junctions based on MgO are discussed.

Fabrication and Noise Performance of Magnetic Tunnel Junctions for Detection of Bio-magnetic Field

Fabrication and Noise Performance of Magnetic Tunnel Junctions for Detection of Bio-magnetic Field

Observation of TaB x O y Along the Ta Diffusion Path Through a Boron and Oxygen Containing Tri-layer Structure

Diffusion and migration of elements are commonly observed in the fabrication of multilayer thin-film devices, including those of STT-RAM. The CoFeB/MgO/CoFeB tri-layer thin-film stack has been widely used in the design of STT-RAM devices as the functional magnetic-tunnel-junction (MTJ) structure. Such issues faced in the fabrication of these devices have been extensively researched from the stand point of engineering the materials property and structure to achieve the best MTJ performance. In this work, we conducted a detailed examination of the chemical-state change of the Ta and B in a CoFeB/MgO/CoFeB/Ta film stack by using x-ray photoelectron spectroscopy (XPS) and time-of-flight secondary ion mass spectrometry. We showed that the chemical-state change of Ta and B is a result of the Ta diffusion phenomena through the CoFeB/MgO/CoFeB tri-layer structure. In particular, we report the evidences of the formation of TaBxOy compound at some considerable depth away from the Ta layer. Also of value to XPS spectroscopy, the Ta binding energy for such TaBxOy compound is reported for the first time.

The Performance of Magnetic Tunnel Junction Integrated on the Back-End Metal Line of Complimentary Metal–Oxide–Semiconductor Circuits

In this paper, we have described the complementary metal–oxide–semiconductor (CMOS)/magnetic tunnel junction (MTJ) integrated process technology; MTJs were fabricated on via metal with surface roughness of 0.3 nm with 0.14 µm CMOS process and 60 ×180 nm2 MTJ process. It is shown that by this process technology, the fabricated MTJ on CMOS logic circuit plane achieves a large change in a resistance of 3.63 kΩ (anti-parallel) with the TMR ratio of 138% at room temperature, which is large enough for a sensing scheme of standard CMOS logic. Furthermore, we have successfully demonstrated the DC and AC operation of this MTJ with write transistors. As the results, our MTJ achieves high enough write/read performance with transistors for realizing MTJ-based logic circuits.

Detection of pinholes in magnetic tunnel junctions by magnetic coupling

Pinholes in tunnel barriers are detrimental to the performance of magnetic tunnel junctions (MTJs) since they create direct magnetic exchange coupling between the free and pinned magnetic films and may act as current short circuits. A simple and straightforward technique which enables observation of pinholes and distinguishes pinhole coupling from orange-peel coupling would aid greatly in optimizing the performance of MTJs. However, the existing methods for this determination are quite complex and destructive and do not work on complete structures. We have developed a simpler, nondestructive method that works on full MTJ structures which is able to identify whether an observed coupling arises primarily from magnetic exchange coupling through pinholes or from orange-peel coupling. The method is based on the shift in the free layer hysteresis loop at low temperatures. It is well known that the shift in the pinned layer loop at low temperatures is due to the sharp increase of the IrMn pinning strength. If pinholes exist, the free layer loop will also exhibit a shift due to direct exchange coupling. If there are no pinholes, no shift will be observed since orange-peel coupling is magnetostatic and cobalt has essentially no increase in magnetization below 300K. In this way, a quick diagnosis can be made of whether or not pinholes exist in the MTJ.